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VIA's KT333 chipset
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| Wed Feb 20, 2002 | 8:34P| PermaLink |
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Bringing DDR333 to AMD's present Socket A platform presents several formidable challenges. First and foremost, the Athlon XP's front-side bus currently runs at only 266MHz, so it can only transfer 2.1GB/s. DDR memory at 333MHz offers as much as 2.7GB/s of bandwidth. Hence the challenge.
Now, that fact alone isn't the end of the matter. The current DDR266 chipsets don't deliver completely on their promise of 2.1GB/s of throughput, so there is a little room for improvement. On top of that, components in the system other than the CPU can make use of extra memory bandwidth, even if the CPU is bottlenecking on its front-side bus. Hard drives and other I/O devices will use direct memory access (DMA) to read and write data to memory without passing data across the front-side bus.
Still, the prospects for performance gains when putting DDR333 memory on a 266MHz front-side bus aren't great. The nastiest part of the problem is that, by definition, the 333MHz memory controller will run out of sync with the 266MHz front-side bus. Running the FSB and memory clocks at different speeds can introduce additional latency into the process of accessing memory, which can offset any performance advantage afforded by the faster memory clock. Add it all up, and the best one can hope for is incremental performance improvements.
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FULL STORY @
TECH-REPORT
(http://www.tech-report.com/reviews/2002q1/via-kt333/index.x?pg=1)
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