The new Celeron will try to anticipate what data a program will need next and pre-load it into the chip's L2 cache. In certain situations-especially on the chips with 512K L2 caches-data prefetch could improve performance. Unfortunately, the Celeron is still gazetted up with a 100MHz front-side bus and good old PC133 memory. It replaces the 0.18-micron core of the present chips available in market. Celeron 1.20 GHz includes includes an integrated on-die, 256KB 8-way set associative level-two (L2) cache. The L2 cache implements the Advanced
Transfer Cache Architecture with a 256-bit wide bus. Celeron 1.20 GHz also includes a 16 KB level one (L1) instruction cache and 16 KB L1 data cache.
These cache arrays run at the full speed of Celeron 1.20 GHz core. The Deep Sleep state is the lowest power state the processor can enter while maintaining context. The Deep Sleep state is entered by stopping the BCLK input (after the Sleep state was entered from the assertion of the
SLP# pin). The processor is in Deep Sleep state immediately after BCLK is stopped. BCLK and BCLK# have to be separated by at least 0.2V during the Deep Sleep State. The Deep Sleep state is the lowest power state the processor can enter while maintaining context. The Deep Sleep state is entered by stopping the BCLK input (after the Sleep state was entered from the assertion of the SLP# pin). The processor is in Deep Sleep state immediately after BCLK is
stopped. BCLK and BCLK# have to be separated by at least 0.2V during the Deep Sleep State.
FULL STORY @ TECHHARD (http://www.techhard.com/docs/pro/cel120/cel120_1.htm)
