Okay, what I'm about to discuss no one should really know. I mean there is knowing your hardware and there's knowing your hardware - this topic falls under the latter :-)
Ever wonder if that RAM you bought is really what you wanted?
Unless the OEM is nice enough to put an inventory sticker on the ram stick with
64, 32, 100, or 133 cryptically in there somewhere, you wouldn't have a clue
what it was you were holding. The same goes for that sick of RAM that was hiding
behind the couch - what speed is it?
The same goes for that sick of RAM that was hiding behind the couch - what speed is it?
How then do you decipher the codes printed on each chip? Well, step one is to go to the manufacturers website and hope they are web-savy enough to have put up decent documentation. I looked around trying to find out what one stick of RAM I have is but wasn't able to find any info on it.
Strangely enough Hyundai (Korean Car maker to most of us) has
such a section on their website. Listed are hundreds of Adobe PDF's that explain
every single bit of code and tell you way more then any normal human should know
about their RAM. Remember HY57V651620B TC-75, cause we're about to explain what
the heck it actually means.
Listed are hundreds of Adobe PDF's that explain every single bit of code and tell you way more then any normal human should know about their RAM. Remember HY57V651620B TC-75, cause we're about to explain what the heck it actually means.
While looking around their site I was able to dig up even more info on my "can I have 64megs of 133Mhz RAM, please". Again this all falls under the category of stuff no human should really know, but its still interesting none the less...
The Hyundai HY57V651620B is a 67,108,864-bit CMOS Synchronous DRAM, ideally suited for the main memory applications which require large memory density and high bandwidth. HY57V651620B is organized as 4banks of 1,048,576x16. HY57V651620B is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL. Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by a single control command (Burst length of 1,2,4,8 or Full page), and the burst count sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)
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